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1 mbit (128k x 8) static ram cy62128ev30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05579 rev. *c revised may 07, 2007 features ? very high speed: 45 ns ? temperature ranges? ? industrial: ?40c to +85c ? automotive-a: ?40c to +85c ? automotive-e: ?40c to +125c ? wide voltage range: 2.20v ? 3.60v ? pin compatible with cy62128dv30 ? ultra low standby power ? typical standby current: 1 a ? maximum standby current: 4 a ? ultra low active power ? typical active current: 1.3 ma @ f = 1 mhz ? easy memory expansion with ce 1 , ce 2 and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? offered in pb-free 32-pin soic, 32-pin tsop i, and 32-pin stsop packages functional description [1] the cy62128ev30 is a high performance cmos static ram module organized as 128k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for prov iding more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic po wer down feature that signifi- cantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce 1 high or ce 2 low). the eight input and output pins (io 0 through io 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or a write operation is in progress (ce 1 low and ce 2 high and we low). to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. data on the eight io pins is then written into the location specified on the address pin (a 0 through a 16 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the io pins. logic block diagram a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 12 sense amps power down we oe a 13 a 14 a 15 a 16 row decoder column decoder 128k x 8 array input buffer a 10 a 11 ce 1 ce 2 note 1. for best practice recommendations, refer to the cypress application note ?system design guidelines? at http://www.cypress.com. [+] feedback [+] feedback
document #: 38-05579 rev. *c page 2 of 11 cy62128ev30 mobl ? pin configuration [2] product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 (a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max cy62128ev30ll ind?l/auto-a 2.2 3.0 3.6 45 1.3 2.0 11 16 1 4 cy62128ev30ll auto-e 2.2 3.0 3.6 55 1.3 4.0 11 35 1 30 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe stsop top view (not to scale) 30 28 29 31 24 19 23 22 21 20 18 13 17 16 15 14 11 12 io 2 io 1 gnd io 7 io 4 io 5 io 6 io 0 ce 1 a 11 a 5 9 10 32 1 2 3 4 5 6 7 8 ce 2 a 15 nc a 10 io 3 a 1 a 0 a 3 a 2 26 25 26 27 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe tsop i top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 io 2 io 1 gnd io 7 io 4 io 5 io 6 io 0 ce 1 a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc a 10 io 3 a 1 a 0 a 3 a 2 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view soic 12 13 29 32 31 30 16 15 17 18 gnd a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 io 7 io 6 io 5 io 4 a 2 nc io 0 io 1 io 2 ce 1 oe a 10 io 3 a 1 a 0 a 11 ce 2 notes: 2. nc pins are not connected on the die. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. [+] feedback [+] feedback
document #: 38-05579 rev. *c page 3 of 11 cy62128ev30 mobl ? maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. ............ .......... 55c to +125c supply voltage to ground potential ....................... .................. ?0.3v to v cc(max) + 0.3v dc voltage applied to outputs in high-z state [4, 5] ......................... ?0.3v to v cc(max) + 0.3v dc input voltage [4,5] ...................... ?0.3v to v cc(max) + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (mil-std-883, method 3015) latch up current..................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62128ev30ll ind?l/auto-a ?40c to +85c 2.2v to 3.6v auto-e ?40c to +125c electrical characteristics (over the operating range) parameter description test conditions 45 ns (ind?l/auto -a) 55 ns (auto-e) unit min typ [3] max min typ [3] max v oh output high voltage i oh = ?0.1 ma 2.0 2.0 v i oh = ?1.0 ma, v cc > 2.70v 2.4 2.4 v v ol output low voltage i ol = 0.1 ma 0.4 0.4 v i ol = 2.1 ma, v cc > 2.70v 0.4 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3v 1.8 v cc + 0.3v v v cc = 2.7v to 3.6v 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?4 +4 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?4 +4 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 11 16 11 35 ma f = 1 mhz 1.3 2.0 1.3 4.0 ma i sb1 automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v v in > v cc ?0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe and we ), v cc = 3.60v 14 135 a i sb2 [7] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 14 130 a capacitance (for all packages) [8] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes: 4. v il(min) = ?2.0v for pulse durations less than 20 ns. 5. v ih(max) = v cc +0.75v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 7. only chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating. 8. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
document #: 38-05579 rev. *c page 4 of 11 cy62128ev30 mobl ? thermal resistance parameter description test conditions tsop i soic stsop unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 33.01 48.67 32.56 c/w jc thermal resistance (junction to case) 3.42 25.86 3.59 c/w ac test loads and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 data retention characteristics (over the operating range) parameter description conditions min typ [3] max unit v dr v cc for data retention 1.5 v i ccdr [7] data retention current v cc = 1.5v, ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v ind?l/auto-a 3 a auto-e 30 a t cdr [8] chip deselect to data retention time 0ns t r [9] operation recovery time t rc ns data retention waveform [10] v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce notes: 9. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 10. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. [+] feedback [+] feedback
document #: 38-05579 rev. *c page 5 of 11 cy62128ev30 mobl ? switching characteristics (over the operating range) [10, 11] parameter description 45 ns (ind?l/auto-a) 55 ns (auto-e) unit min max min max read cycle t rc read cycle time 45 55 ns t aa address to data valid 45 55 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 45 55 ns t doe oe low to data valid 22 25 ns t lzoe oe low to low z [12] 55ns t hzoe oe high to high z [12,13] 18 20 ns t lzce ce low to low z [12] 10 10 ns t hzce ce high to high z [12, 13] 18 20 ns t pu ce low to power up 00ns t pd ce high to power up 45 55 ns write cycle [14] t wc write cycle time 45 55 ns t sce ce low to write end 35 40 ns t aw address setup to write end 35 40 ns t ha address hold from write end 0 0 ns t sa address setup to write start 0 0 ns t pwe we pulse width 35 40 ns t sd data setup to write end 25 25 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [12, 13] 18 20 ns t lzwe we high to low z [12] 10 10 ns notes: 11. test conditions for all parameters other than tri-state parameter s assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 12. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 13. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 14. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hol d timing should be referenced to the edge of the signal that t erminates the write. [+] feedback [+] feedback
document #: 38-05579 rev. *c page 6 of 11 cy62128ev30 mobl ? switching waveforms read cycle 1 (address transition controlled) [15, 16] read cycle no. 2 (oe controlled) [10, 16, 17] write cycle no. 1 (we controlled) [10, 15, 18, 19] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data io oe note 20 notes: 15. the device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 16. we is high for read cycle. 17. address valid before or similar to ce 1 transition low and ce 2 transition high. 18. data io is high impedance if oe = v ih . 19. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 20. during this period, the ios are in output state. do not apply input signals. [+] feedback [+] feedback
document #: 38-05579 rev. *c page 7 of 11 cy62128ev30 mobl ? write cycle no. 2 (ce1 or ce2 controlled) [10, 14, 18, 19] write cycle no. 3 (we controlled, oe low) [10, 19] truth table ce 1 ce 2 we oe inputs/outputs mode power h x x x high z deselect/power down standby (i sb ) x l x x high z deselect/power down standby (i sb ) l h h l data out read active (i cc ) l h h h high z output disabled active (i cc ) l h l x data in write active (i cc ) switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data io we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data io note 20 [+] feedback [+] feedback
document #: 38-05579 rev. *c page 8 of 11 cy62128ev30 mobl ? ordering information speed (ns) ordering code package diagram package type operating range 45 CY62128EV30LL-45SXI 51-85081 32-pin 450 -mil soic (pb-free) industrial cy62128ev30ll-45zxi 51-85056 32-pin tsop type i (pb-free) cy62128ev30ll-45zaxi 51-85094 32-pin stsop (pb-free) 45 cy62128ev30ll-45zxa 51-85056 32-pin tsop type i (pb-free) automotive-a 55 cy62128ev30ll-55zxe 51-85056 32-pin tsop type i (pb-free) automotive-e contact your local cypress sales repres entative for availability of these parts. package diagrams figure 1. 32-pin (450 mil) molded soic, 51-85081 0.546[13.868] 0.440[11.176] 0.101[2.565] 0.050[1.270] 0.014[0.355] 0.118[2.997] 0.004[0.102] 0.047[1.193] 0.006[0.152] 0.023[0.584] 0.793[20.142] 0.450[11.430] 0.566[14.376] 0.111[2.819] 0.817[20.751] bsc. 0.020[0.508] min. max. 0.012[0.304] 0.039[0.990] 0.063[1.600] seating plane 1 16 17 32 0.004[0.102] 51-85081-*b [+] feedback [+] feedback
document #: 38-05579 rev. *c page 9 of 11 cy62128ev30 mobl ? figure 2. 32-pin thin small outline package type i (8 x 20 mm), 51-85056 package diagrams (continued) 51-85056-*d [+] feedback [+] feedback
cy62128ev30 mobl ? document #: 38-05579 rev. *c page 10 of 11 ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under pate nt or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express writt en agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support system s where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 3. 32-pin shrunk thin small outline package (8 x 13.4 mm), 51-85094 mobl is a registered trademark, and more battery life is a trademark, of cypre ss semiconductor. all product and company names mentioned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 51-85094-*d [+] feedback [+] feedback
document #: 38-05579 rev. *c page 11 of 11 cy62128ev30 mobl ? document history page document title: cy62128ev30 mobl ? 1 mbit (128k x 8) static ram document number: 38-05579 rev. ecn no. issue date orig. of change description of change ** 285473 see ecn pci new data sheet *a 461631 see ecn nxr converted from preliminary to final removed 35 ns speed bin removed ?l? version of cy62128ev30 removed reverse tsop i package from product offering. changed i cc (typ) from 8 ma to 11 ma and i cc (max) from 12 ma to 16 ma for f = f max changed i cc (max) from 1.5 ma to 2.0 ma for f = 1 mhz changed i sb2 (max) from 1 a to 4 a changed i sb2 (typ) from 0.5 a to 1 a changed i ccdr (max) from 1 a to 3 a changed the ac test load capacitance value from 50 pf to 30 pf changed t lzoe from 3 to 5 ns changed t lzce from 6 to 10 ns changed t hzce from 22 to 18 ns changed t pwe from 30 to 35 ns changed t sd from 22 to 25 ns changed t lzwe from 6 to 10 ns updated the ordering information table. *b 464721 see ecn nxr updated the block diagram on page # 1 *c 1024520 see ecn vkn added final automotive-a and automotive-e information added footnote #9 related to i sb2 and i ccdr updated ordering information table [+] feedback [+] feedback

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